1. Field of the Invention
The present invention relates to a method of generating a test pattern for an integrated circuit, and more particularly to a method of generating a test pattern used in conducting a test using a boundary scan system.
2. Description of the Prior Art
FIG. 19 shows an example of an integrated circuit using a boundary scan system. In an integrated circuit 100 of FIG. 19, common data applied to input terminals 101A through 101D is applied to an internal circuit 104 through input buffers 102A through 102D and boundary scan cells 103A through 103D. The internal circuit 104 is a logical circuit including various gates, etc. The data from the internal circuit 104 is applied to output terminals 106A through 106D through boundary scan cells 103E through 103H and output buffers 105A through 105D.
In the boundary scan system, a connection state between the integrated circuits 100 can be easily tested after the implementation of each integrated circuit 100 on aboard. The test can be conducted as follows. That is, when the test is conducted, the boundary scan cells 103A through 103H are set in a shift mode. Then, test data is applied to an input terminal 107A. The test data is sequentially transmitted in a shifting operation of the boundary scan cells 103A through 103H through an input buffer 108A. Thus, the test data is first set in the boundary scan cells 103E through 103H on the output side of the integrated circuit 100.
When the test data is completely set, a test clock is applied to the boundary scan cells 103E through 103H. Thus, the boundary scan cells 103E through 103H apply the test data to the output terminals 106A through 106D through the output buffers 105A through 105D. The output data applied to the output terminals 106A through 106D reaches the input terminal of the integrated circuit at the next stage through the wiring on the board. In the integrated circuit at the next stage, the test data received by the input terminal is stored in the corresponding boundary scan cell. The integrated circuit at the next stage transfers the stored test data in the shifting operation as in the integrated circuit 100, and serially outputs the data from the output terminal.
When the output data matches the test data applied to the integrated circuit 100, it proves that a successful wiring is set between the integrated circuit 100 and the integrated circuit at the next stage on the board. On the other hand, if the output data does not match the test data applied to the integrated circuit 100, then it is determined that the wiring between the integrated circuit 100 and the integrated circuit at the next stage on the board is defective. Thus, in the boundary scan system, the connection state between integrated circuits can be easily tested after the implementation of each integrated circuit on the board regardless of the type of the internal circuit 104 in the integrated circuit 100.
The defective wiring between integrated circuits on the board can be: an input value of the integrated circuit on the input side fixed to a grounding potential regardless of an output value of the integrated circuit on the output side; an input value of the integrated circuit on the input side fixed to the potential of the power supply regardless of an output value of the integrated circuit on the output side; etc. Therefore, it is easy to understand that two types of tests should be conducted in the above described test. That is, it is determined whether or not the output of “all 0” is correctly transmitted, and whether or not the output of “all 1” is correctly transmitted.
However, the following problem occurs if it is determined whether or not the output of “all 1” is correctly transmitted immediately after the determination as to whether or not the output of “all 0” is correctly transmitted. That is, since each boundary scan cell is designed in most cases such that its output value cannot be changed in the shift mode, the output buffers 105A through 105D are simultaneously inverted when control exits the shift mode if “1” is input to the boundary scan cells 103E through 103H in the shifting operation with the output value of “0” held in each of the boundary scan cells 103E through 103H. At this time, a large electric current flows through the output buffers 105A through 105D, and generates noise in the power supply and ground. The simultaneous inversion of the output buffers 105A through 105D does not occur in the normal operation. Such noise as is not generated in the normal operation, but is generated by such a large electric current may produce defective test data, thereby interfering a correct test.
As a method of solving the problem, there is a method of delaying the data from the boundary scan cells 103E through 103H by different delay times as described in Japanese Patent Application Laid-Open No. 5-129912. According to the technology, even if the data of the test results from the boundary scan cells 103E through 103H simultaneously change, each of the output buffers 105A through 105D sequentially transmits the data from the boundary scan cells 103E through 103H to the output terminals 106A through 106D based on the delay times. As a result, no large electric current flows through the output buffers 105A through 105D, thereby solving the problem that the noise is generated on the power supply and ground.
However, the above described conventional technology has the following problem. That is, to delay the data from the boundary scan cells 103E through 103H, there should be delay elements having different delay times to be inserted between the boundary scan cells 103E through 103H and the output buffers 105A through 105D. As a result, the integrated circuit 100 becomes undesirably large.